library IEEE;
use IEEE.std_logic_1164.all;

entity DataOutput is
  Port (--Data Signals
        Data : out std_logic_vector(15 downto 0);
        --Output Signals
        PCLK : out std_logic;
        ROW_CLK : out std_logic;
        HSYNC : out std_logic;
        VSYNC : out std_logic;
        --Input Signals
        RESET : in std_logic;
        PWDN : in std_logic;        
        --Control Signals
        I2C_DATA : inout std_logic;
        I2C_CLK : inout std_logic;
        --Misc. Signals
        MISCIO : out std_logic_vector(5 downto 0));
end DataOutput;
